The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
Aug. 14, 2008
Pooja M. Kotecha, Beacon, NY (US);
Frank J. Musante, Poughkeepsie, NY (US);
Veena S. Pureswaran, Raleigh, NC (US);
Louise H. Trevillyan, Katonah, NY (US);
Paul G. Villarrubia, Austin, TX (US);
Pooja M. Kotecha, Beacon, NY (US);
Frank J. Musante, Poughkeepsie, NY (US);
Veena S. Pureswaran, Raleigh, NC (US);
Louise H. Trevillyan, Katonah, NY (US);
Paul G. Villarrubia, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.