The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2011

Filed:

Jun. 15, 2005
Applicants:

Fan Zhang, Singapore, SG;

Kho Liep Chok, Cupertino, CA (US);

Alex See, Singapore, SG;

Cheng-cheh Tan, Singapore, SG;

Xiaomei Bu, Singapore, SG;

Tae Jong Lee, Singapore, SG;

Liang Choo Hsia, Singapore, SG;

Inventors:

Fan Zhang, Singapore, SG;

Kho Liep Chok, Cupertino, CA (US);

Alex See, Singapore, SG;

Cheng-Cheh Tan, Singapore, SG;

Xiaomei Bu, Singapore, SG;

Tae Jong Lee, Singapore, SG;

Liang Choo Hsia, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.


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