The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Nov. 12, 2008
Mou-shiung Lin, Hsinchu, TW;
Shih-hsiung Lin, Hsinchu, TW;
Hsin-jung Lo, Taipei County, TW;
Ying-chih Chen, Tainan County, TW;
Chiu-ming Chou, Kaohsiung, TW;
Mou-Shiung Lin, Hsinchu, TW;
Shih-Hsiung Lin, Hsinchu, TW;
Hsin-Jung Lo, Taipei County, TW;
Ying-Chih Chen, Tainan County, TW;
Chiu-Ming Chou, Kaohsiung, TW;
Megica Corporation, Hsinchu, TW;
Abstract
A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.