The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Mar. 12, 2008
Timothy H. Daubenspeck, Colchester, VT (US);
Jeffrey P. Gambino, Westford, VT (US);
Christopher D. Muzzy, Burlington, VT (US);
Wolfgang Sauter, Richmond, VT (US);
Jeffrey S. Zimmerman, Swanton, VT (US);
Timothy H. Daubenspeck, Colchester, VT (US);
Jeffrey P. Gambino, Westford, VT (US);
Christopher D. Muzzy, Burlington, VT (US);
Wolfgang Sauter, Richmond, VT (US);
Jeffrey S. Zimmerman, Swanton, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.