The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Mar. 31, 2008
Christopher James Kapusta, Delanson, NY (US);
Donald Cunningham, Dallas, TX (US);
Richard Joseph Saia, Niskayuna, NY (US);
Kevin Durocher, Waterford, NY (US);
Joseph Iannotti, Glenville, NY (US);
William Hawkins, Rexford, NY (US);
Christopher James Kapusta, Delanson, NY (US);
Donald Cunningham, Dallas, TX (US);
Richard Joseph Saia, Niskayuna, NY (US);
Kevin Durocher, Waterford, NY (US);
Joseph Iannotti, Glenville, NY (US);
William Hawkins, Rexford, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.