The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2011
Filed:
Mar. 20, 2008
Yi-wen Chen, Tainan County, TW;
Li-wei Cheng, Hsin-Chu, TW;
Che-hua Hsu, Hsin-Chu Hsien, TW;
Chih-hao Yu, Tainan County, TW;
Cheng-hsien Chou, Tainan, TW;
Chien-ming Lai, Tainan County, TW;
Tian-fu Chiang, Taipei, TW;
Chien-ting Lin, Hsin-Chu, TW;
Guang-hwa MA, Hsinchu, TW;
Yi-Wen Chen, Tainan County, TW;
Li-Wei Cheng, Hsin-Chu, TW;
Che-Hua Hsu, Hsin-Chu Hsien, TW;
Chih-Hao Yu, Tainan County, TW;
Cheng-Hsien Chou, Tainan, TW;
Chien-Ming Lai, Tainan County, TW;
Tian-Fu Chiang, Taipei, TW;
Chien-Ting Lin, Hsin-Chu, TW;
Guang-Hwa Ma, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.