The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
Jan. 08, 2008
Anil Kumar Chinthakindi, Wappingers Falls, NY (US);
Douglas Duane Coolbaugh, Essex Junction, VT (US);
Keith Edward Downes, Stowe, VT (US);
Ebenezer E. Eshun, Wappingers Falls, NY (US);
Zhong-xiang He, Essex Junction, VT (US);
Robert Mark Rassel, Colchester, VT (US);
Anthony Kendall Stamper, Williston, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
Anil Kumar Chinthakindi, Wappingers Falls, NY (US);
Douglas Duane Coolbaugh, Essex Junction, VT (US);
Keith Edward Downes, Stowe, VT (US);
Ebenezer E. Eshun, Wappingers Falls, NY (US);
Zhong-Xiang He, Essex Junction, VT (US);
Robert Mark Rassel, Colchester, VT (US);
Anthony Kendall Stamper, Williston, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.