The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2011

Filed:

Jun. 29, 2007
Applicants:

Jae-sung Roh, Ichon-shi, KR;

Kee-jeung Lee, Ichon-shi, KR;

Han-sang Song, Ichon-shi, KR;

Seung-jin Yeom, Ichon-shi, KR;

Deok-sin Kil, Ichon-shi, KR;

Young-dae Kim, Ichon-shi, KR;

Jin-hyock Kim, Ichon-shi, KR;

Inventors:

Jae-Sung Roh, Ichon-shi, KR;

Kee-Jeung Lee, Ichon-shi, KR;

Han-Sang Song, Ichon-shi, KR;

Seung-Jin Yeom, Ichon-shi, KR;

Deok-Sin Kil, Ichon-shi, KR;

Young-Dae Kim, Ichon-shi, KR;

Jin-Hyock Kim, Ichon-shi, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial layer is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer and the sacrificial layer are then removed.

Published as:

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