The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2011

Filed:

Feb. 22, 2006
Applicants:

Anil K. Chinthakindi, Poughkeepsie, NY (US);

Douglas D. Coolbaugh, Essex Junction, VT (US);

Keith E. Downes, Stowe, VT (US);

Ebenezer E. Eshun, Newburgh, NY (US);

John E. Florkey, Centerville, OH (US);

Heidi L. Greer, Essex Junction, VT (US);

Robert M. Rassel, Colchester, VT (US);

Anthony K. Stamper, Williston, VT (US);

Kunal Vaed, Poughkeepsie, NY (US);

Inventors:

Anil K. Chinthakindi, Poughkeepsie, NY (US);

Douglas D. Coolbaugh, Essex Junction, VT (US);

Keith E. Downes, Stowe, VT (US);

Ebenezer E. Eshun, Newburgh, NY (US);

John E. Florkey, Centerville, OH (US);

Heidi L. Greer, Essex Junction, VT (US);

Robert M. Rassel, Colchester, VT (US);

Anthony K. Stamper, Williston, VT (US);

Kunal Vaed, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.


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