The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Nov. 17, 2008
Anil K. Chinthakindi, Poughkeepsie, NY (US);
Douglas D. Coolbaugh, Essex Junction, VT (US);
John M. Cotte, New Fairfield, CT (US);
Ebenezer E. Eshun, Essex Junction, VT (US);
Zhong-xiang He, Essex Junction, VT (US);
Anthony K. Stamper, Williston, VT (US);
Eric J. White, Charlotte, VT (US);
Anil K. Chinthakindi, Poughkeepsie, NY (US);
Douglas D. Coolbaugh, Essex Junction, VT (US);
John M. Cotte, New Fairfield, CT (US);
Ebenezer E. Eshun, Essex Junction, VT (US);
Zhong-Xiang He, Essex Junction, VT (US);
Anthony K. Stamper, Williston, VT (US);
Eric J. White, Charlotte, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.