The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2011
Filed:
Feb. 11, 2009
Igor Arsovski, Williston, VT (US);
Hayden C. Cranford, Jr., Cary, NC (US);
Joseph A. Iadanza, Hinesburg, VT (US);
Todd E. Leonard, Williston, VT (US);
Jason M. Norman, Essex Junction, VT (US);
Hemen R. Shah, South Burlington, VT (US);
Sebastian T. Ventrone, South Burlington, VT (US);
Igor Arsovski, Williston, VT (US);
Hayden C. Cranford, Jr., Cary, NC (US);
Joseph A. Iadanza, Hinesburg, VT (US);
Todd E. Leonard, Williston, VT (US);
Jason M. Norman, Essex Junction, VT (US);
Hemen R. Shah, South Burlington, VT (US);
Sebastian T. Ventrone, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.