The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2011

Filed:

Mar. 21, 2008
Applicants:

In-young Lee, Gyunggi-do, KR;

Ho-jin Lee, Seoul, KR;

Hyun-soo Chung, Gyunggi-do, KR;

Ju-il Choi, Gyunggi-do, KR;

Son-kwan Hwang, Gyunggi-do, KR;

Inventors:

In-Young Lee, Gyunggi-do, KR;

Ho-Jin Lee, Seoul, KR;

Hyun-Soo Chung, Gyunggi-do, KR;

Ju-Il Choi, Gyunggi-do, KR;

Son-Kwan Hwang, Gyunggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.


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