The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2011
Filed:
Jun. 30, 2008
Jack Hwang, Portland, OR (US);
Sridhar Govindaraju, Hillsboro, OR (US);
Karson Knutson, Beaverton, OR (US);
Harold Kennel, Portland, OR (US);
Aravind Killampalli, Hillsboro, OR (US);
Jack Hwang, Portland, OR (US);
Sridhar Govindaraju, Hillsboro, OR (US);
Karson Knutson, Beaverton, OR (US);
Harold Kennel, Portland, OR (US);
Aravind Killampalli, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.