The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2011
Filed:
Aug. 02, 2005
Kuang Kian Ong, Singapore, SG;
Kin Leong Pey, Singapore, SG;
King Jien Chui, Singapore, SG;
Ganesh Samudra, Singapore, SG;
Yee Chia Yeo, Singapore, SG;
Yung Fu Chong, Singapore, SG;
Kuang Kian Ong, Singapore, SG;
Kin Leong Pey, Singapore, SG;
King Jien Chui, Singapore, SG;
Ganesh Samudra, Singapore, SG;
Yee Chia Yeo, Singapore, SG;
Yung Fu Chong, Singapore, SG;
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Abstract
A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.