The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Dec. 04, 2008
Chen-liang Chu, Hsin-Chu, TW;
Chun-ting Liao, Hsin-Chu, TW;
Tsung-yi Huang, Hsin-Chu, TW;
Fei-yuh Chen, Hsin-Chu, TW;
Chen-Liang Chu, Hsin-Chu, TW;
Chun-Ting Liao, Hsin-Chu, TW;
Tsung-Yi Huang, Hsin-Chu, TW;
Fei-Yuh Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.