The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Nov. 14, 2008
Kuang Kian Ong, Singapore, SG;
Sai Hooi Yeong, Singapore, SG;
Kin Leong Pey, Singapore, SG;
Lap Chan, Singapore, SG;
Yung Fu Chong, Singapore, SG;
Kuang Kian Ong, Singapore, SG;
Sai Hooi Yeong, Singapore, SG;
Kin Leong Pey, Singapore, SG;
Lap Chan, Singapore, SG;
Yung Fu Chong, Singapore, SG;
Nanyang Technological University, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
National University Of Singapore, Singapore, SG;
Abstract
A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.