The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Aug. 26, 2008
Chien-ting Lin, Hsin-Chu, TW;
Li-wei Cheng, Hsin-Chu, TW;
Jung-tsung Tseng, Tainan, TW;
Che-hua Hsu, Hsin-Chu Hsien, TW;
Chih-hao Yu, Tainan County, TW;
Tian-fu Chiang, Taipei, TW;
Yi-wen Chen, Tainan County, TW;
Chien-ming Lai, Tainan County, TW;
Cheng-hsien Chou, Tainan, TW;
Chien-Ting Lin, Hsin-Chu, TW;
Li-Wei Cheng, Hsin-Chu, TW;
Jung-Tsung Tseng, Tainan, TW;
Che-Hua Hsu, Hsin-Chu Hsien, TW;
Chih-Hao Yu, Tainan County, TW;
Tian-Fu Chiang, Taipei, TW;
Yi-Wen Chen, Tainan County, TW;
Chien-Ming Lai, Tainan County, TW;
Cheng-Hsien Chou, Tainan, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.