The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Jan. 29, 2008
James W. Adkisson, Jericho, VT (US);
Natalie B. Feilchenfeld, Jericho, VT (US);
Jeffrey P. Gambino, Westford, VT (US);
Howard S. Landis, Underhill, VT (US);
Benjamin T. Voegeli, Burlington, VT (US);
Steven H. Voldman, South Burlington, VT (US);
Michael J. Zierak, Essex Junction, VT (US);
James W. Adkisson, Jericho, VT (US);
Natalie B. Feilchenfeld, Jericho, VT (US);
Jeffrey P. Gambino, Westford, VT (US);
Howard S. Landis, Underhill, VT (US);
Benjamin T. Voegeli, Burlington, VT (US);
Steven H. Voldman, South Burlington, VT (US);
Michael J. Zierak, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.