The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Oct. 05, 2007
Leonard Forbes, Corvallis, OR (US);
Paul A. Farrar, Okatie, SC (US);
Arup Bhattacharyya, Essex Junction, VT (US);
Hussein I. Hanafi, Basking Ridge, NJ (US);
Warren M. Farnworth, Nampa, ID (US);
Leonard Forbes, Corvallis, OR (US);
Paul A. Farrar, Okatie, SC (US);
Arup Bhattacharyya, Essex Junction, VT (US);
Hussein I. Hanafi, Basking Ridge, NJ (US);
Warren M. Farnworth, Nampa, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.