The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Nov. 12, 2008
John J. Benoit, Williston, VT (US);
David S. Collins, Williston, VT (US);
Natalie B. Feilchenfeld, Jericho, VT (US);
Michael L. Gautsch, Jericho, VT (US);
Xuefeng Liu, South Burlington, VT (US);
Robert M. Rassel, Colchester, VT (US);
Stephen A. St. Onge, Colchester, VT (US);
James A. Slinkman, Montpelier, VT (US);
John J. Benoit, Williston, VT (US);
David S. Collins, Williston, VT (US);
Natalie B. Feilchenfeld, Jericho, VT (US);
Michael L. Gautsch, Jericho, VT (US);
Xuefeng Liu, South Burlington, VT (US);
Robert M. Rassel, Colchester, VT (US);
Stephen A. St. Onge, Colchester, VT (US);
James A. Slinkman, Montpelier, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.