The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2010

Filed:

Apr. 10, 2007
Applicants:

Tsuyoshi Yamamoto, Kariya, JP;

Toshio Sakakibara, Nishio, JP;

Hiroki Nakamura, Handa, JP;

Toshiyuki Morishita, Nagoya, JP;

Takasumi Ooyanagi, Hitachinaka, JP;

Atsuo Watanabe, Hitachiota, JP;

Inventors:

Tsuyoshi Yamamoto, Kariya, JP;

Toshio Sakakibara, Nishio, JP;

Hiroki Nakamura, Handa, JP;

Toshiyuki Morishita, Nagoya, JP;

Takasumi Ooyanagi, Hitachinaka, JP;

Atsuo Watanabe, Hitachiota, JP;

Assignees:

DENSO CORPORATION, Kariya, JP;

Hitachi Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.


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