The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
May. 19, 2006
Moshe E. Preil, Sunnyvale, CA (US);
Jun YE, Palo Alto, CA (US);
James N. Wiley, Menlo Park, CA (US);
Shauh-teh Juang, Saratoga, CA (US);
Michael J. Gassner, San Jose, CA (US);
Moshe E. Preil, Sunnyvale, CA (US);
Jun Ye, Palo Alto, CA (US);
James N. Wiley, Menlo Park, CA (US);
Shauh-Teh Juang, Saratoga, CA (US);
Michael J. Gassner, San Jose, CA (US);
ASML Netherlands B.V., Veldhoven, NL;
Abstract
One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.