The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
May. 26, 2009
Applicants:
Lucian Shifren, Hillsboro, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Steven M. Cea, Hillsboro, OR (US);
Cory E. Weber, Hillsboro, OR (US);
Justin K. Brask, Portland, OR (US);
Inventors:
Lucian Shifren, Hillsboro, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Steven M. Cea, Hillsboro, OR (US);
Cory E. Weber, Hillsboro, OR (US);
Justin K. Brask, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/425 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.