The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2010

Filed:

May. 30, 2007
Applicants:

Sriram Muthukumar, Chandler, AZ (US);

Raul Mancera, Chandler, AZ (US);

Yoshihiro Tomita, Ibaraki, JP;

Chi-won Hwang, Ibaraki, JP;

Inventors:

Sriram Muthukumar, Chandler, AZ (US);

Raul Mancera, Chandler, AZ (US);

Yoshihiro Tomita, Ibaraki, JP;

Chi-won Hwang, Ibaraki, JP;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.


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