The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
Sep. 27, 2007
Yong-soo Kim, Ichon-shi, KR;
Hong-seon Yang, Ichon-shi, KR;
Se-aug Jang, Ichon-shi, KR;
Seung-ho Pyi, Ichon-shi, KR;
Kwon Hong, Ichon-shi, KR;
Heung-jae Cho, Ichon-shi, KR;
Kwan-yong Lim, Ichon-shi, KR;
Min-gyu Sung, Ichon-shi, KR;
Seung-ryong Lee, Ichon-shi, KR;
Tae-yoon Kim, Ichon-shi, KR;
Yong-Soo Kim, Ichon-shi, KR;
Hong-Seon Yang, Ichon-shi, KR;
Se-Aug Jang, Ichon-shi, KR;
Seung-Ho Pyi, Ichon-shi, KR;
Kwon Hong, Ichon-shi, KR;
Heung-Jae Cho, Ichon-shi, KR;
Kwan-Yong Lim, Ichon-shi, KR;
Min-Gyu Sung, Ichon-shi, KR;
Seung-Ryong Lee, Ichon-shi, KR;
Tae-Yoon Kim, Ichon-shi, KR;
Hynix Semiconductor Inc., Icheon-si, KR;
Abstract
A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.