The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2010
Filed:
Oct. 28, 2008
Scott A. Hareland, Tigard, OR (US);
Robert S. Chau, Beaverton, OR (US);
Brian S. Doyle, Portland, OR (US);
Rafael Rios, Portland, OR (US);
Tom Linton, San Jose, CA (US);
Suman Datta, Beaverton, OR (US);
Scott A. Hareland, Tigard, OR (US);
Robert S. Chau, Beaverton, OR (US);
Brian S. Doyle, Portland, OR (US);
Rafael Rios, Portland, OR (US);
Tom Linton, San Jose, CA (US);
Suman Datta, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.