The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2010
Filed:
Oct. 11, 2006
Yun-yu Wang, Poughquag, NY (US);
Christopher D. Sheraw, Poughkeepsie, NY (US);
Anthony G. Domenicucci, New Paltz, NY (US);
Linda Black, Wappingers Falls, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
David M. Fried, Brewster, NY (US);
Yun-Yu Wang, Poughquag, NY (US);
Christopher D. Sheraw, Poughkeepsie, NY (US);
Anthony G. Domenicucci, New Paltz, NY (US);
Linda Black, Wappingers Falls, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
David M. Fried, Brewster, NY (US);
International Business Machines Corporation, Armonk, NY (US);
GlobalFoundries, Inc, Grand Cayman, KY;
Abstract
Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.