The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2010

Filed:

Jan. 15, 2008
Applicants:

Kazutaka Koshiishi, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Satoshi Isa, Tokyo, JP;

Inventors:

Kazutaka Koshiishi, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Satoshi Isa, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Chuo-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge of the high dielectric loss tangent layer is preferably separated by a predetermined distance or more from the edge of the power-supply plane or the edge of the ground plane which is located on the inner side.


Find Patent Forward Citations

Koshiishi, Kazutaka. (2010). Semiconductor device including ground and power-supply planes and a dielectric layer between the ground and power-supply planes (U.S. Patent No. 7816768). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7816768

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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