The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Jan. 23, 2008
Chih-hao Yu, Tainan County, TW;
Li-wei Cheng, Hsin-Chu, TW;
Tian-fu Chiang, Taipei, TW;
Cheng-hsien Chou, Tainan, TW;
Chien-ting Lin, Hsin-Chu, TW;
Che-hua Hsu, Hsin-Chu Hsien, TW;
Guang-hwa MA, Hsinchu, TW;
Chih-Hao Yu, Tainan County, TW;
Li-Wei Cheng, Hsin-Chu, TW;
Tian-Fu Chiang, Taipei, TW;
Cheng-Hsien Chou, Tainan, TW;
Chien-Ting Lin, Hsin-Chu, TW;
Che-Hua Hsu, Hsin-Chu Hsien, TW;
Guang-Hwa Ma, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.