The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2010

Filed:

Dec. 04, 2009
Applicants:

Philip Lyndon R. Cablao, Singapore, SG;

Dario S. Filoteo, Jr., Singapore, SG;

Emmanuel A. Espiritu, Singapore, SG;

Leo A. Merilo, Singapore, SG;

Inventors:

Philip Lyndon R. Cablao, Singapore, SG;

Dario S. Filoteo, Jr., Singapore, SG;

Emmanuel A. Espiritu, Singapore, SG;

Leo A. Merilo, Singapore, SG;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/02 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.


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