The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Sep. 13, 2004
Chih-hsiang Yao, Taipei, TW;
Tai-chun Huang, Hsinchu, TW;
Kuan-shou Chi, Hsin-Chu, TW;
Chih-cherng Jeng, Hsin-Chu, TW;
Ming-shuoh Liang, Hsin-Chu, TW;
Wen-kai Wan, Hsin-Chu, TW;
Chin-chiu Hsia, Taipei, TW;
Chih-Hsiang Yao, Taipei, TW;
Tai-Chun Huang, Hsinchu, TW;
Kuan-Shou Chi, Hsin-Chu, TW;
Chih-Cherng Jeng, Hsin-Chu, TW;
Ming-Shuoh Liang, Hsin-Chu, TW;
Wen-Kai Wan, Hsin-Chu, TW;
Chin-Chiu Hsia, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-chu, TW;
Abstract
A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.