The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2010
Filed:
Feb. 08, 2008
Kyoichi Suguro, Yokohama, JP;
Kiyotaka Miyano, Yokohama, JP;
Ichiro Mizushima, Yokohama, JP;
Yoshitaka Tsunashima, Yokohama, JP;
Takayuki Hiraoka, Sagamihara, JP;
Yasushi Akasaka, Yokohama, JP;
Tsunetoshi Arikado, Tokyo, JP;
Kyoichi Suguro, Yokohama, JP;
Kiyotaka Miyano, Yokohama, JP;
Ichiro Mizushima, Yokohama, JP;
Yoshitaka Tsunashima, Yokohama, JP;
Takayuki Hiraoka, Sagamihara, JP;
Yasushi Akasaka, Yokohama, JP;
Tsunetoshi Arikado, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;
Abstract
A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.