The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2010

Filed:

Mar. 09, 2007
Applicants:

Atsushi Yagishita, Yokohama, JP;

Kouji Matsuo, Yokohama, JP;

Yasushi Akasaka, Yokohama, JP;

Kyoichi Suguro, Yokohama, JP;

Yoshitaka Tsunashima, Yokohama, JP;

Inventors:

Atsushi Yagishita, Yokohama, JP;

Kouji Matsuo, Yokohama, JP;

Yasushi Akasaka, Yokohama, JP;

Kyoichi Suguro, Yokohama, JP;

Yoshitaka Tsunashima, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.


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