The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2010
Filed:
Oct. 20, 2009
Hamza Yilmaz, Saratoga, CA (US);
Daniel Calafut, San Jose, CA (US);
Steven Sapp, Felton, CA (US);
Nathan Kraft, Pottsville, PA (US);
Ashok Challa, Sandy, UT (US);
Hamza Yilmaz, Saratoga, CA (US);
Daniel Calafut, San Jose, CA (US);
Steven Sapp, Felton, CA (US);
Nathan Kraft, Pottsville, PA (US);
Ashok Challa, Sandy, UT (US);
Fairchild Semiconductor Corporatiion, South Portland, ME (US);
Abstract
A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.