The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Oct. 03, 2007
Yasuo Yamaguchi, Tokyo, JP;
Shigeto Maegawa, Tokyo, JP;
Takashi Ipposhi, Tokyo, JP;
Toshiaki Iwamatsu, Tokyo, JP;
Shigenobu Maeda, Tokyo, JP;
Yuuichi Hirano, Tokyo, JP;
Takuji Matsumoto, Tokyo, JP;
Shoichi Miyamoto, Tokyo, JP;
Yasuo Yamaguchi, Tokyo, JP;
Shigeto Maegawa, Tokyo, JP;
Takashi Ipposhi, Tokyo, JP;
Toshiaki Iwamatsu, Tokyo, JP;
Shigenobu Maeda, Tokyo, JP;
Yuuichi Hirano, Tokyo, JP;
Takuji Matsumoto, Tokyo, JP;
Shoichi Miyamoto, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.