The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Oct. 12, 2004
Joseph C. Fjelstad, Maple Valley, WA (US);
Para K. Segaram, Brookfield, AU;
Thomas J. Obenhuber, San Francisco, CA (US);
Inessa Obenhuber, Legal Representative, San Francisco, CA (US);
Kevin P. Grundy, Fremont, CA (US);
William F. Wiedemann, Campbell, CA (US);
Joseph C. Fjelstad, Maple Valley, WA (US);
Para K. Segaram, Brookfield, AU;
Thomas J. Obenhuber, San Francisco, CA (US);
Inessa Obenhuber, legal representative, San Francisco, CA (US);
Kevin P. Grundy, Fremont, CA (US);
William F. Wiedemann, Campbell, CA (US);
Interconnect Portfolio LLC, Cupertino, CA (US);
Abstract
A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.