The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2010

Filed:

Apr. 10, 2008
Applicants:

Chen-bau Wu, Zhubei, TW;

Chien-shao Tang, Hsinchu, TW;

Robin Hsieh, Hsin Chu, TW;

Ruey-hsin Liu, Hsin-Chu, TW;

Shun-liang Hsu, Hsin-Chu, TW;

Inventors:

Chen-Bau Wu, Zhubei, TW;

Chien-Shao Tang, Hsinchu, TW;

Robin Hsieh, Hsin Chu, TW;

Ruey-Hsin Liu, Hsin-Chu, TW;

Shun-Liang Hsu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.


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