The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Aug. 28, 2007
Kazuhiko Ooi, Nagano, JP;
Tadashi Kodaira, Nagano, JP;
Eisaku Watari, Nagano, JP;
Jyunichi Nakamura, Nagano, JP;
Shunichiro Matsumoto, Nagano, JP;
Kazuhiko Ooi, Nagano, JP;
Tadashi Kodaira, Nagano, JP;
Eisaku Watari, Nagano, JP;
Jyunichi Nakamura, Nagano, JP;
Shunichiro Matsumoto, Nagano, JP;
Shinko Electric Industries Co., Ltd., Nagano, JP;
Abstract
To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.