The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Oct. 31, 2007
Shreesh Narasimha, Beacon, NY (US);
Paul David Agnello, Wappingers Falls, NY (US);
Xiaomeng Chen, Poughkeepsie, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Mukesh Vijay Khare, White Plains, NY (US);
Byeong Y. Kim, Lagrangeville, NY (US);
Devandra K. Sadana, Pleasantville, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Paul David Agnello, Wappingers Falls, NY (US);
Xiaomeng Chen, Poughkeepsie, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Mukesh Vijay Khare, White Plains, NY (US);
Byeong Y. Kim, Lagrangeville, NY (US);
Devandra K. Sadana, Pleasantville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.