The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Feb. 27, 2007
Mitsuaki Katagiri, Tokyo, JP;
Satoshi Nakamura, Tokyo, JP;
Takashi Suga, Tokyo, JP;
Yoji Nishio, Tokyo, JP;
Satoshi Isa, Tokyo, JP;
Satoshi Itaya, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Satoshi Nakamura, Tokyo, JP;
Takashi Suga, Tokyo, JP;
Yoji Nishio, Tokyo, JP;
Satoshi Isa, Tokyo, JP;
Satoshi Itaya, Tokyo, JP;
Elpida Memory, Tokyo, JP;
Abstract
A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.