The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Feb. 15, 2005
Applicants:
Michael Brennan, Campbell, CA (US);
Jaeyong Park, Sunnyvale, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Satoshi Torii, Sunnyvale, CA (US);
Inventors:
Michael Brennan, Campbell, CA (US);
Jaeyong Park, Sunnyvale, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Satoshi Torii, Sunnyvale, CA (US);
Assignee:
Spansion LLC, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract
A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.