The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2010
Filed:
Aug. 29, 2006
Mitsuaki Katagiri, Tokyo, JP;
Satoshi Nakamura, Yokohama, JP;
Takashi Suga, Yokohama, JP;
Satoshi Isa, Tokyo, JP;
Yoji Nishio, Tokyo, JP;
Seiji Funaba, Tokyo, JP;
Yukitoshi Hirose, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Satoshi Nakamura, Yokohama, JP;
Takashi Suga, Yokohama, JP;
Satoshi Isa, Tokyo, JP;
Yoji Nishio, Tokyo, JP;
Seiji Funaba, Tokyo, JP;
Yukitoshi Hirose, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.