The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2010
Filed:
Dec. 05, 2007
Sameer Jain, Beacon, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Karen A. Nummy, Newburgh, NY (US);
Viorel Ontalus, Danbury, CT (US);
Jang H. Sim, Hopewell Junction, NY (US);
Sameer Jain, Beacon, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Karen A. Nummy, Newburgh, NY (US);
Viorel Ontalus, Danbury, CT (US);
Jang H. Sim, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.