The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Jun. 26, 2008
Satoru Akiyama, Kokubunji, JP;
Takao Watanabe, Fuchu, JP;
Yuichi Matsui, Koganei, JP;
Masahiko Hiratani, Kokubunji, JP;
Satoru Akiyama, Kokubunji, JP;
Takao Watanabe, Fuchu, JP;
Yuichi Matsui, Koganei, JP;
Masahiko Hiratani, Kokubunji, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A memory cell capacitor (C) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.