The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Sep. 13, 2007
Mitsuaki Katagiri, Tokyo, JP;
Satoshi Nakamura, Tokyo, JP;
Takashi Suga, Tokyo, JP;
Hiroya Shimizu, Tokyo, JP;
Satoshi Isa, Tokyo, JP;
Satoshi Itaya, Tokyo, JP;
Yukitoshi Hirose, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Satoshi Nakamura, Tokyo, JP;
Takashi Suga, Tokyo, JP;
Hiroya Shimizu, Tokyo, JP;
Satoshi Isa, Tokyo, JP;
Satoshi Itaya, Tokyo, JP;
Yukitoshi Hirose, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.