The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Jul. 28, 2006
Hung Der Su, Sheh-Chung Village, TW;
Ju-wang Hsu, Taipei, TW;
Yi-chun Huang, Pingjhen, TW;
Shien-yang Wu, Hsin-Chu, TW;
Yung-shun Chen, Hsin-Chu, TW;
Tung-heng Shie, Hsinchu, TW;
Yuan-hung Chiu, Taipei, TW;
Jyh-huei Chen, Hsinchu, TW;
Jhon Jhy Liaw, Hsin-Chu, TW;
Hung Der Su, Sheh-Chung Village, TW;
Ju-Wang Hsu, Taipei, TW;
Yi-Chun Huang, Pingjhen, TW;
Shien-Yang Wu, Hsin-Chu, TW;
Yung-Shun Chen, Hsin-Chu, TW;
Tung-Heng Shie, Hsinchu, TW;
Yuan-Hung Chiu, Taipei, TW;
Jyh-Huei Chen, Hsinchu, TW;
Jhon Jhy Liaw, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.