The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
May. 20, 2009
Cha-won Koh, Yongin-si, KR;
Byung-hong Chung, Seoul, KR;
Sang-gyun Woo, Yongin-si, KR;
Jeong-lim Nam, Yongin-si, KR;
Seok-hwan OH, Suwon-si, KR;
Jai-hyuk Song, Seoul, KR;
Hyun Park, Hwaseong-si, KR;
Yool Kang, Seongnam-si, KR;
Cha-Won Koh, Yongin-si, KR;
Byung-Hong Chung, Seoul, KR;
Sang-Gyun Woo, Yongin-si, KR;
Jeong-Lim Nam, Yongin-si, KR;
Seok-Hwan Oh, Suwon-si, KR;
Jai-Hyuk Song, Seoul, KR;
Hyun Park, Hwaseong-si, KR;
Yool Kang, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.