The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2010

Filed:

Oct. 17, 2007
Applicants:

Roger A. Booth, Jr., Wappingers Falls, NY (US);

Maryjane Brodsky, Salt Point, NY (US);

Kangguo Cheng, Beacon, NY (US);

Chengwen Pei, Danbury, CT (US);

Inventors:

Roger A. Booth, Jr., Wappingers Falls, NY (US);

MaryJane Brodsky, Salt Point, NY (US);

Kangguo Cheng, Beacon, NY (US);

Chengwen Pei, Danbury, CT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/106 (2006.01); H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.


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