The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Feb. 12, 2008
Do-jae Yoo, Seoul, KR;
Young-do Kweon, Seoul, KR;
Seog-moon Choi, Seoul, KR;
Burn-sik Jang, Seongnam-si, KR;
Tae-sung Jeong, Hwaseong-si, KR;
Do-Jae Yoo, Seoul, KR;
Young-Do Kweon, Seoul, KR;
Seog-Moon Choi, Seoul, KR;
Burn-Sik Jang, Seongnam-si, KR;
Tae-Sung Jeong, Hwaseong-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration.