The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2009
Filed:
Dec. 28, 2005
Daniel C. Edelstein, White Plains, NY (US);
Panayotis C. Andricacos, Croton-on-Hudson, NY (US);
John M. Cotte, New Fairfield, CT (US);
Hariklia Deligianni, Tenafly, NJ (US);
John H. Magerlein, Yorktown Heights, NY (US);
Kevin S. Petrarca, Newburgh, NY (US);
Kenneth J. Stein, Sandy Hook, CT (US);
Richard P. Volant, New Fairfield, CT (US);
Daniel C. Edelstein, White Plains, NY (US);
Panayotis C. Andricacos, Croton-on-Hudson, NY (US);
John M. Cotte, New Fairfield, CT (US);
Hariklia Deligianni, Tenafly, NJ (US);
John H. Magerlein, Yorktown Heights, NY (US);
Kevin S. Petrarca, Newburgh, NY (US);
Kenneth J. Stein, Sandy Hook, CT (US);
Richard P. Volant, New Fairfield, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.